1. Field of the Invention
The present invention relates generally to digital data processing systems, and more particularly, relates to bus architectures for communication amongst individual components of digital data processing systems with a symmetric parallel multi-processing bus architecture.
2. Description to the Prior Art
The simplest method of coupling individual components of a data processing system conceptually is using point-to-point connections. Using this technique, each component may communicate with each other component on a noninterference basis over any convenient format. U.S. Pat. No. 4,514,823 issued to Mendelson et al., describes one of many formats available for point-to-point communication.
As the number of devices which must intercommunicate becomes relatively large, it becomes more economical to have multiple devices share a common communication bus. The primary advantage of the bus architecture is that an individual device is able to communicate with a large number of different devices using a single, shared interface (i.e. the bus interface). The disadvantage of the bus architecture is that the bus becomes a resource which must be shared by a potentially large number of users. If more than one user needs to use the bus at the same time, a scheme needs to be developed which arbitrates or awards use of the bus to one of the multiple requestors based upon priority or some other factor.
Most bus arbitration techniques employ a centralized bus controller or arbiter. This function is often collocated with a particular one of the devices using the bus (e.g., a central processor, an input/output controller, etc.). U.S. Pat. No. 4,375,639 issued to Johnson Jr. discusses a bus arbitration scheme based on the use of a "master" device located on the bus. Embodying the bus arbitration function within a microprocessor is shown in U.S. Pat. No. 4,580,213 issued to Hulett et al.
A major disadvantage of a bus architecture system having a centralized arbiter is in the area of fault tolerance. For that reason, U.S. Pat. No. 4,402,040 issued to Evett discusses a bus architecture wherein the arbitration function is distributed amongst the individual devices using the bus. U.S. Pat. No. 4,620,278 issued to Ellsworth et al., describes another approach to distribution of the arbitration function. In either case, however, the activity of the individual devices must be synchronized to perform the arbitration function.
The necessity to synchronize distributed bus arbitration has resulted in prior art systems in which interrupt signals tend to be processed as discrete point-to-point communications, because interrupts are by nature asynchronous. This means that separate point-to-point interrupt interfaces are required.